1. Field of the Invention
The present invention relates to circuit design, and more particularly, to a method and an apparatus for verifying logic and the representation of a circuit design in a front-end stage.
2. Description of the Related Art
The design of a semiconductor integrated circuit can be divided into a front-end design stage that includes logic design and circuit design, and a back-end design stage that includes layout design. In the front-end design stage, a designer designs a logic circuit using a hardware description language (hereinafter, referred to as HDL) and verifies the functions of the logic circuit using automatic design verification tools. After verifying the required functions of the logic circuit, the designer performs the back-end design stage, creating a gate level or transistor level circuit corresponding to the verified logic circuit designed with the HDL.
FIG. 1 is a block diagram showing the stages of designing a logic circuit using a conventional method.
Referring to FIG. 1, the design stages 100 of the logic circuit include a logic circuit design stage 110, a logic circuit verification stage 120, and a defect correction stage 130.
In the design stage 110, at least one of a register transfer level (RTL) source code, a gate level net-list, and a net-list for a simulation program with integrated circuit emphasis (hereinafter, referred to as SPICE) corresponding to the logic circuit to be designed is selected and generated.
The verification stage 120 verifies the function of the logic circuit, which is defined in the design stage 110 using a simulation method. Generally, an assertion-based verification (hereinafter, referred to as ABV) method is used to verify a logic circuit that is generated in RTL or HDL source code. The ABV inserts an assertion that calls an assertion specification macro module into the part of the HDL source code to be verified. Thereafter, a specification macro processor converts the assertion specification macro module into HDL code, and defects of the logic circuit including the HDL code of the converted macro module are detected using a logic simulator, such as a Verilog simulator. If the logic circuit is generated using a gate level net-list or SPICE net-list, the assertion-based verification method cannot be used, and the function of the logic circuit is verified using a different simulator apart from the assertion-based verification method.
Defects detected in the verification stage 120 are corrected by modifying the logic circuit 120 in the defect correction stage 130.
The verification stage 120 using the conventional ABV method illustrated in FIG. 1 has the following problems.
Although the ABV verification method is quite useful for HDL code-based circuit design, it cannot be used for designing a circuit at the logic gate or transistor level.
The assertion used in the ABV only verifies the function of the logic circuit, without considering the timing and analog signal characteristics.
Since the assertion specification macro module can be used only for a specific ABV logic simulator, the type of logic simulator which can be used is limited.
Since the ABV method is linked to the simulator, the verification takes a long time, because the assertion is inserted into many parts of the HDL source code, and the operations of the assertion must be performed in series.